HD64F2149 Datasheet, PDF (392/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.6.3 Contention between TCOR Write and Compare-Match
During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match
occurs and the compare-match signal is disabled. Figure 12.15 shows this operation.
With TMRX, an ICR input capture contends with a compare-match in the same way as with a
write to TCORC. In this case, the input capture has priority and the compare-match signal is
inhibited.
TCOR write cycle by CPU
T₁
T₂
ø
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
Compare-match signal
TCOR write data
Inhibited
Figure 12.15 Contention between TCOR Write and Compare-Match
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