HD64F2149 Datasheet, PDF (507/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16 clocks
8 clocks
0
7
15 0
7
Internal base
clock
15 0
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Start bit
D0
D1
Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode
Thus the receive margin in asynchronous mode is given by equation (1) below.
M = 0.5 – ¹ – (L – 0.5)F – ^{D – 0.5} (1 + F) × 100%
2N
N
.......... (1)
Where M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by
equation (2) below.
When D = 0.5 and F = 0,
M=
0.5
–
2
1
× 16
× 100%
= 46.875%
.......... (2)
However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in
system design.
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