HD64F2149 Datasheet, PDF (622/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18B.2.4 LPC Channel 3 Address Register (LADR3)
LADR3H
LADR3L
Bit
Initial value
Read/Write
7 65 43 21 07 65 43 21 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — Bit 1 TWRE
0 00 00 00 00 00 00 00 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓
↓
IDR3, ODR3, _{Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 1/0 Bit 1 0}
STR3 address
↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓
TWR0–TWR15 _{Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 1/0 1/0 1/0 1/0}
address
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address
setting and control the operation of the two-way registers. The contents of the address field in
LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
LADR3 is initialized to H'0000 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
LADR3H Bits 7 to 0: Channel 3 Address Bits 15 to 8
LADR3L Bits 7 to 3 and 1: Channel 3 Address Bits 7 to 3 and 1
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of
LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 of LADR3 is regarded
as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4
of LADR3 is inverted, and the values of bits 3 to 0 are ignored. Register selection according to the
bits ignored in address match determination is as shown in the following table.
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