HD64F2149 Datasheet, PDF (640/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

LCLK
LFRAME
LAD3–LAD0
Start
ADDR
Cycle type,
direction,
and size
TAR Sync
Slave must stop driving
Too many Syncs
cause timeout
Master will
drive high
Figure 18B.3 Abort Mechanism
18B.3.3 A20 Gate
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under
firmware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 4) to 1 in
HICR0 (H'FE40).
Note: * An Intel microprocessor
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1
command followed by data. When the slave processor (H8S/2149) receives data, it normally uses
an interrupt routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1
command, firmware copies bit 1 of the data and outputs it at the gate A20 pin.
Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a
fast A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. When the DDR
bit for P81 is set to 1, the state of the P81/GA20 pin can be monitored by reading the GA20 bit in
HICR2. The initial output from this pin will be a logic 1, which is the initial value. Afterward,
the host processor can manipulate the output from this pin by sending commands and data. This
function is only available via the IDR1 register. The host interface decodes commands input from
the host. When an H'D1 host command is detected, bit 1 of the data following the host command
is output from the GA20 output pin. This operation does not depend on firmware or interrupts,
and is faster than the regular processing using interrupts. Table 18B.3 shows the conditions that
set and clear GA20 (P81). Figure 18B.4 shows the GA20 output in flowchart form. Table 18B.4
indicates the GA20 output signal values.
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