HD6417750RF240DV Datasheet, PDF (943/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 21 High-performance User Debug Interface (H-UDI)
21.3 Operation
21.3.1 TAP Control
Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state
transitions specified by JTAG.
• The transition condition is the TMS value at the rising edge of TCK.
• The TDI value is sampled at the rising edge of TCK, and shifted at the falling edge.
• The TDO value changes at the falling edge of TCK. When not in the Shift-DR or Shift-IR
state, TDO is in the high-impedance state.
• In a transition to TRST = 0, a transition is made to the Test-Logic-Reset state asynchronously
with respect to TCK.
1 Test-Logic-Reset
0
0
1
Run-Test/Idle
1
Select-DR-Scan
0
1 _Capture-DR
0
Shift-DR
0
1
1
Exit1-DR
0
Pause-DR
0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR-Scan
0
1 _Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR
0
1
0
Exit2-IR
1
Update-IR
1
0
Figure 21.2 TAP Control State Transition Diagram
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 891 of 1076