HD6417750RF240DV Datasheet, PDF (785/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length.
Bit 3: STOP
Description
0
1 stop bit^*1
(Initial value)
1
2 stop bits^*2
Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
before it is sent.
2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on-
chip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64,
according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 16.2.8, Bit Rate Register (SCBRR2).
Bit 1: CKS1 Bit 0: CKS0
0
0
1
1
0
1
Note: Pck: Peripheral clock
Description
Pck clock
Pck/4 clock
Pck/16 clock
Pck/64 clock
(Initial value)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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