HD6417750RF240DV Datasheet, PDF (208/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 5 Exceptions
SH7750, SH7750S, SH7750R Group
5.5.2 Exception Source Acceptance
A priority ranking is provided for all exceptions for use in determining which of two or more
simultaneously generated exceptions should be accepted. Five of the general exceptions—the
general illegal instruction exception, slot illegal instruction exception, general FPU disable
exception, slot FPU disable exception, and unconditional trap exception—are detected in the
process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These
exceptions therefore all have the same priority. General exceptions are detected in the order of
instruction execution. However, exception handling is performed in the order of instruction flow
(program order). Thus, an exception for an earlier instruction is accepted before that for a later
instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013