HD6417750RF240DV Datasheet, PDF (254/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 6 Floating-Point Unit (FPU)
SH7750, SH7750S, SH7750R Group
Details
Definitions: The data patterns that cause the problem are defined below. Item (A) to (D) in the
tables correspond to the following data patterns.
• Double-precision denormalized number (A)
H'00000000_XXXXXXXX or H'80000000_XXXXXXXX (X: 0 or 1)
However, H'XXXXXXXX != H'00000000
• Double-precision denormalized number (B)
H'000YYYYY_XXXXXXXX or H'800YYYYY_XXXXXXXX (X: 0 or 1)
However, H'YYYYY != H'00000
• Double-precision qNaN (C)
However, H'XXXXXXXX != H'00000000
• Double-precision qNaN (D)
Note: As defined
H'7FFXXXXX_XXXXXXXX or H'FFFXXXXX_XXXXXXXX (X: 0 or 1)
However, H'XXXXX_XXXXXXXX != H'00000_00000000
Incorrect Operation Results: Table 6.3 lists instructions and data combinations that produce
incorrect operation results when FPSCR.DN = I'b0 (mode in which denormalized numbers are
treated as denormalized numbers).
Input items (A) to (C) are the data patterns defined in “Definitions” above, and problem types (1)
to (7) correspond to the incorrect operation results classified in tables 6.4 to 6.6.
The incorrect operation results for problem types (1), (2), (3), and (7) are zero or infinity.
In problem types (4), (5), and (6), an FPU error exception trap is generated and no value is output
for qNaN.
Case (a) corresponds to problem types (1), (2), and (3); case (b) corresponds to (7); and case (c)
corresponds to (4), (5), and (6).
Page 202 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013