HD6417750RF240DV Datasheet, PDF (184/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 4 Caches
SH7750, SH7750S, SH7750R Group
2. IC address array write (non-associative)
The tag and V bit specified in the data field are written to the IC entry corresponding to the
entry set in the address field. The A bit in the address field should be cleared to 0.
3. IC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tag stored in the
entry specified in the address field is compared with the tag specified in the data field. If the
MMU is enabled at this time, comparison is performed after the virtual address specified by
data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses
match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In
other cases, no operation is performed. This operation is used to invalidate a specific IC entry.
If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an
interrupt is not generated, no operation is performed, and the write is not executed. If an
instruction TLB multiple hit exception occurs during address translation, processing switches
to the instruction TLB multiple hit exception handling routine.
31
24 23
Address field _{1 1 1 1 0 0 0 0}
13 12
Entry
543210
A
31
10 9
10
Data field
Tag
V
Legend:
V: Validity bit
A: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.8 Memory-Mapped IC Address Array
4.5.2 IC Data Array
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is
specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2]
are used for the longword data specification in the entry. As only longword access is used, 0
should be specified for address field bits [1:0].
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Sep 24, 2013