HD6417750RF240DV Datasheet, PDF (401/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 12 Timer Unit (TMU)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the external clock input
edge when an external clock is selected or the input capture function is used in channels 0 to 2.
Bit 4: CKEG1
0
1
Bit 3: CKEG0
0
1
X
Note: X: 0 or 1 (don't care)
Description
Count/input capture register set on rising edge (Initial value)
Count/input capture register set on falling edge
Count/input capture register set on both rising and falling
edges
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): These bits select the TCNT count clock.
With channels 0 to 2, when the on-chip RTC output clock is selected as the count clock for a
channel, that channel can operate even in module standby mode. When another clock is selected,
the channel does not operate in standby mode.
Bit 2: TPSC2
0
1
Bit 1: TPSC1
0
1
0
1
Bit 0: TPSC0
0
1
0
1
0
1
0
1
Description
Counts on Pck/4
(Initial value)
Counts on Pck/16
Counts on Pck/64
Counts on Pck/256
Counts on Pck/1024
Reserved (Do not set)
Counts on on-chip RTC output clock
(Do not set this pattern for channel 3 or 4)
Counts on external clock
(Do not set this pattern for channel 3 or 4)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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