HD6417750RF240DV Datasheet, PDF (284/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 8 Pipelining
SH7750, SH7750S, SH7750R Group
1. General Pipeline
I
D
EX
• Instruction fetch
• Instruction
• Operation
decode
• Issue
• Register read
• Destination address calculation
for PC-relative branch
2. General Load/Store Pipeline
I
D
EX
• Instruction fetch
• Instruction
decode
• Issue
• Register read
• Address
calculation
NA
• Non-memory
data access
MA
• Memory
data access
3. Special Pipeline
I
D
• Instruction fetch
• Instruction
decode
• Issue
• Register read
SX
• Operation
NA
• Non-memory
data access
4. Special Load/Store Pipeline
I
D
• Instruction fetch
• Instruction
decode
• Issue
• Register read
5. Floating-Point Pipeline
SX
• Address
calculation
MA
• Memory
data access
I
D
• Instruction fetch • Instruction
decode
• Issue
• Register read
F1
F2
• Computation 1 • Computation 2
6. Floating-Point Extended Pipeline
I
D
• Instruction fetch
• Instruction
decode
• Issue
• Register read
7. FDIV/FSQRT Pipeline
F0
F1
• Computation 0 • Computation 1
F3
Computation: Takes several cycles
S
• Write-back
S
• Write-back
S
• Write-back
S
• Write-back
FS
• Computation 3
• Write-back
F2
• Computation 2
FS
• Computation 3
• Write-back
Figure 8.1 Basic Pipelines
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013