HD6417750RF240DV Datasheet, PDF (164/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 4 Caches
SH7750, SH7750S, SH7750R Group
Table 4.2 Cache Features (SH7750R)
Item
Capacity
Type
Line size
Entries
Write method
Replacement method
Instruction Cache
Operand Cache
16-Kbyte cache
32-Kbyte cache or 16-Kbyte cache
+ 16-Kbyte RAM
2-way set-associative
2-way set-associative
32 bytes
32 bytes
256 entries/way
512 entries/way
Copy-back/write-through selectable
LRU (least-recently-used) algorithm LRU algorithm
Table 4.3 Features of Store Queues
Item
Capacity
Addresses
Write
Write-back
Access right
Store Queues
2 × 32 bytes
H'E000 0000 to H'E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction (PREF instruction)
MMU off: according to MMUCR.SQMD
MMU on: according to individual page PR
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013