HD6417750RF240DV Datasheet, PDF (35/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Edge Detection), DACK (Read Cycle)................................................................. 589
Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ
(Level Detection), DACK (Read Cycle)................................................................ 590
Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ
(Edge Detection), DACK (Read Cycle)................................................................. 591
Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) →
External Bus .......................................................................................................... 592
Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI
(Level Detection)................................................................................................... 593
Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Level Detection)................................................................................................... 594
Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Edge Detection).................................................................................................... 595
Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ
(Level Detection)................................................................................................... 596
Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ
(Edge Detection).................................................................................................... 597
Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ
(Level Detection)/32-Byte Block Transfer
(Bus Width: 64 Bits, SDRAM: Row Hit Write) .................................................... 598
Figure 14.23 On-Demand Transfer Mode Block Diagram ......................................................... 603
Figure 14.24 System Configuration in On-Demand Data Transfer Mode .................................. 605
Figure 14.25 Data Transfer Request Format............................................................................... 606
Figure 14.26 Single Address Mode: Synchronous DRAM → External Device Longword Transfer
SDRAM auto-precharge Read bus cycle, burst
(RCD[1:0] = 01, CAS latency = 3, TPC[2:0] = 001).................................................. 609
Figure 14.27 Single Address Mode: External Device → Synchronous DRAM Longword Transfer
SDRAM auto-precharge Write bus cycle, burst
(RCD[1:0] = 01, TRWL[2:0] = 101, TPC[2:0] = 001)............................................... 610
Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer ........... 611
Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer .......................................... 612
Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer .......................................... 613
Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit
Transfer/Channel 0 On-Demand Data Transfer..................................................... 614
Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit
Transfer/Channel 0 On-Demand Data Transfer..................................................... 615
Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) .... 616
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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