HD6417750RF240DV Datasheet, PDF (465/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
13.2.10 Synchronous DRAM Mode Register (SDMR)
The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is
written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3
synchronous DRAM.
Settings for the SDMR register must be made before accessing synchronous DRAM.
Bit: 15
14
13
12
11
10
9
8
Initial value: —
—
—
—
—
—
—
—
R/W: W
W
W
W
W
W
W
W
Bit: 7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: W
W
W
W
W
W
W
W
Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register,
if the value to be set is “X” and the SDMR register address is “Y”, value “X” is written to the
synchronous DRAM mode register by performing a write to address X + Y. When the
synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to
A2 of this LSI, and A1 of the synchronous DRAM is connected to A3 of this LSI, the value
actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right.
For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address
H'FF900000 (address “Y”) + H'08C0 (value “X”) (= H'FF9008C0). As a result, H'0230 is written
to the SDMR register. The range of value “X” is H'0000 to H'0FFC.
Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address
H'FF940000 (address “Y”) + H'08C0 (value “X”) (= H'FF9408C0). As a result, H'0230 is written
to the SDMR register. The range of value “X” is H'0000 to H'0FFC.
The lower 16 bits of the address are set in the synchronous DRAM mode register.
When the bus width is 32 bits, the burst length is 4* and 8. When the bus width is 64 bits, the burst
length is fixed at 4. When a setting is made in SDMR, byte-size writes are performed at the
following addresses.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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