HD6417750RF240DV Datasheet, PDF (631/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
In dual address mode, data corresponding to the size specified by CHCRn.TS is read from the
transfer source in the data read cycle, and, in the data write cycle, it is transferred in two bus
cycles in order to write in the transfer destination the data corresponding to the size specified by
CHCRn.TS. In this process, the transfer data is temporarily stored in the data buffer in the bus
state controller (BSC).
In a transfer between external memories such as that shown in figure 14.7, data is read from
external memory into the BSC's data buffer in the read cycle, then written to the other external
memory in the write cycle. Figure 14.8 shows the timing for this operation. The DACK output
timing is the same as that of CSn in a read or write cycle specified by the CHCRn.AM bit.
DMAC
SAR
DAR
Memory
Transfer source
module
BSC ^{Data buffer}
Transfer destination
module
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the bus state controller (BSC).
1st bus cycle
DMAC
SAR
DAR
Memory
Transfer source
module
BSC Data buffer
Transfer destination
module
Taking the DAR value as the address, the data stored in the BSC's data buffer is
written to the transfer destination module.
2nd bus cycle
Figure 14.7 Operation in Dual Address Mode
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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