HD6417750RF240DV Datasheet, PDF (40/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/
Hold Time Insertion, AnS = 1, AnH = 1) .............................................................. 959
Figure 22.19 Burst ROM Bus Cycle (No Wait) ......................................................................... 960
Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;
2nd/3rd/4th Data: One Internal Wait).................................................................... 961
Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion,
AnS = 1, AnH = 1) ................................................................................................ 962
Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ........................ 963
Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single
(RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) ........................................... 964
Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01,
CAS Latency = 3, TPC[2:0] = 011)....................................................................... 965
Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,
Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3) .......................................... 966
Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands,
Burst ((RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3).............. 967
Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst
((RASD = 1, CAS Latency = 3) ............................................................................ 968
Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single
(RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010).......................................... 969
Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst
(RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010).......................................... 970
Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,
Burst (RASD = 1, RCD[1:0] = 01, TRWL[2:0] = 010)......................................... 971
Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands,
Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010).............. 972
Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command,
Burst (RASD = 1, TRWL[2:0] = 010)................................................................... 973
Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command
(RASD = 1, TPC[2:0] = 001) ................................................................................ 974
Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh
(TRAS = 1, TRC[2:0] = 001) ................................................................................ 975
Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh
(TRC[2:0] = 001)................................................................................................... 976
Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting
(PALL)............................................................................................................. 977
Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting
(SET)................................................................................................................ 978
Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001
(2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010.......................................... 979
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013