HD6417750RF240DV Datasheet, PDF (157/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 3 Memory Management Unit (MMU)
3.7.3 ITLB Data Array 2
ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry
is selected by bits [9:8].
In the data field, SA is indicated by bits [2:0], and TC by bit [3].
The following two kinds of operation can be used on ITLB data array 2:
1. ITLB data array 2 read
SA and TC are read into the data field from the ITLB entry corresponding to the entry set in
the address field.
2. ITLB data array 2 write
SA and TC specified in the data field are written to the ITLB entry corresponding to the entry
set in the address field.
31
24 23
Address field _{1 1 1 1 0 0 1 1 1}
10 9 8 7
0
E
31
Data field
4320
SA
Legend:
TC: Timing control bit
E: Entry
TC
SA: Space attribute bits
: Reserved bits (0 write value, undefined read value)
Figure 3.15 Memory-Mapped ITLB Data Array 2
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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