HD6417750RF240DV Datasheet, PDF (716/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 15 Serial Communication Interface (SCI)
SH7750, SH7750S, SH7750R Group
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.9, Bit Rate Register (SCBRR1).
Bit 1: CKS1 Bit 0: CKS0
0
0
1
1
0
1
Note: Pck: Peripheral clock
Description
Pck clock
Pck/4 clock
Pck/16 clock
Pck/64 clock
(Initial value)
15.2.6 Serial Control Register (SCSCR1)
Bit: 7
6
5
TIE
RIE
TE
Initial value: 0
0
0
R/W: R/W R/W R/W
4
3
2
1
0
RE MPIE TEIE CKE1 CKE0
0
0
0
0
0
R/W R/W R/W R/W R/W
The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock
output in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCSCR1 can be read or written to by the CPU at all times.
SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and
the TDRE flag in SCSSR1 is set to 1.
Bit 7: TIE
Description
0
Transmit-data-empty interrupt (TXI) request disabled*
(Initial value)
1
Transmit-data-empty interrupt (TXI) request enabled
Note: * TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it
to 0, or by clearing the TIE bit to 0.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013