HD6417750RF240DV Datasheet, PDF (499/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
13.3.4 DRAM Interface
Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to
100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The
DRAM interface function can then be used to connect DRAM to this LSI.
16, 32, or 64 bits can be selected as the interface data width for area 3 when bits DRAMTP2–0 are
set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits DRAMTP2–0 are set
to 101.
2-CAS 16-bit DRAMs can be connected, since CAS is used to control byte access.
Signals used for connection when DRAM is connected to area 3 are RAS, CAS0 to CAS7, and
RD/WR. CAS2 to CAS7 are not used when the data width is 16 bits. When DRAM is connected
to areas 2 and 3, the signals for area 2 DRAM connection are RAS2, CAS4 to CAS7, and RD/WR,
and those for area 3 DRAM connection are RAS, CAS0 to CAS3, and RD/WR.
In addition to normal read and write access modes, fast page mode is supported for burst access.
For DRAM connected to areas 2 and 3, EDO mode, which enables the DRAM access time to be
increased, is supported.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 447 of 1076