HD6417750RF240DV Datasheet, PDF (771/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 15 Serial Communication Interface (SCI)
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data
SCSSR1 Status Flags
Receive Errors
RDRF ORER FER
Overrun error
1
1
0
Framing error
0
0
1
Parity error
0
0
0
Overrun error + framing error
1
1
1
Overrun error + parity error
1
1
0
Framing error + parity error
0
0
1
Overrun error + framing error +
1
1
1
parity error
Legend:
O: Receive data is transferred from SCRSR1 to SCRDR1.
X: Receive data is not transferred from SCRSR1 to SCRDR1.
PER
0
0
1
0
1
1
1
Receive Data
Transfer
SCRSR1 → SCRDR1
X
O
O
X
X
O
X
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that the SCI
receiver continues to operate in the break state, so if the FER flag is cleared to 0 it will be set to 1
again.
Sending a Break Signal: The input/output condition and level of the TxD pin are determined by
bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send
a break signal.
After the serial transmitter is initialized, the TxD pin function is not selected and the value of the
SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled).
The SPB0IO and SPB0DT bits should therefore be set to 1 (designating output and high level)
beforehand.
To send a break signal during serial transmission, clear the SPB0DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of its current state, and the TxD pin becomes an output port
outputting the value 0.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 719 of 1076