HD6417750RF240DV Datasheet, PDF (178/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 4 Caches
SH7750, SH7750S, SH7750R Group
Note: This includes a break triggered by a debugging tool swapping an instruction (a break
occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped
for an instruction).
Condition 4: A store instruction (MOV, FMOV, AND.B, OR, B, XOR.B, MOVCA.L, STC.L, or
STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four
instructions after the instruction associated with the exception or interrupt described
in condition 3. This includes cases where the store instruction that accesses internal
RAM itself generates an exception.
Description: When the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary
that includes an address that differs by H'2000 from the address accessed by the store instruction
that accesses internal RAM mentioned in condition 4. For example, when a long word is stored at
address H'7C000204, the 8 bytes of data in the internal RAM mapped to addresses H'7C002200 to
H'7C002207 becomes corrupted.
Examples
Example 1 A store instruction accessing internal RAM occurs within four instructions after an
instruction generating a TLB miss exception.
MOV.L #H'0C400000, R0
R0 is an address causing a TLB miss.
MOV.L #H'7C000204, R1
R1 is an address mapped to internal RAM.
MOV.L @R0, R2
TLB miss exception occurs.
NOP
1st word
NOP
2nd word
NOP
3rd word
MOV.L R3, @R1
Store instruction accessing internal RAM
Example 2 A store instruction accessing internal RAM occurs within four instructions after an
instruction causing an interrupt to be accepted.
MOV.L #H'7C002000, R1
R1 is an address mapped to internal RAM.
MOV.L #H'12345678, R0
An interrupt is accepted after this instruction.
NOP
1st word
NOP
2nd word
NOP
3rd word
MOV.L R0, @R1
Store instruction accessing internal RAM
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013