HD6417750RF240DV Datasheet, PDF (433/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
13.2.2 Bus Control Register 2 (BCR2)
Bus control register 2 (BCR2) is a 16-bit readable/writable register that specifies the bus width for
each area, and whether a 16-bit port is used.
BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in
standby mode. External memory space other than area 0 should not be accessed until register
initialization is completed.
Bit: 15
A0SZ1
Initial value: 0/1*
R/W: R
14
A0SZ0
0/1*
R
13
A6SZ1
1
R/W
12
A6SZ0
1
R/W
11
A5SZ1
1
R/W
10
A5SZ0
1
R/W
9
A4SZ1
1
R/W
8
A4SZ0
1
R/W
Bit: 7
6
5
4
3
2
1
0
A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A0SZ0 — PORTEN
Initial value: 1
1
1
1
1
1
0
0
R/W: R/W R/W R/W R/W R/W R/W
—
R/W
Note: * These bits sample the values of the external pins that specify the area 0 bus size.
Bits 15 and 14—Area 0 Bus Width (A0SZ1, A0SZ0): These bits sample the external pins, MD4
and MD3 that specify the bus size in a power-on reset by the RESET pin. They are read-only bits.
Bit 15
A0SZ1
0
1
Bit 14
A0SZ0
0
1
0
1
Description
Bus width is 64 bits
Bus width is 8 bits
Bus width is 16 bits
Bus width is 32 bits
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 381 of 1076