HD6417750RF240DV Datasheet, PDF (415/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
Name
Signals
I/O
Description
Master/slave
switchover
MD7/TXD
I/O
Indicates master/slave status in a power-on reset.^*4
Serial interface TXD
DMAC0
acknowledge
signal
DACK0
O
DMAC channel 0 data acknowledge
DMAC1
acknowledge
signal
DACK1
O
DMAC channel 1 data acknowledge
Read/column
address strobe/
cycle frame 2
RD2
O
Same signal as RD/CASS/FRAME
This signal is used when the RD/CASS/FRAME
signal load is heavy.
Read/write 2
RD/WR2
O
Same signal as RD/WR
This signal is used when the RD/WR signal load is
heavy.
Notes: 1. MD3/CE2A input/output switching is performed by BCR1.A56PCM. Output is selected
when BCR1.A56PCM = 1.
2. MD4/CE2B input/output switching is performed by BCR1.A56PCM. Output is selected
when BCR1.A56PCM = 1.
3. MD5/RAS2 input/output switching is performed by BCR1.DRAMTP. Output is selected
when BCR1.DRAMTP (2–0) = 101.
4. In a power-on reset by means of the RESET pin.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 363 of 1076