HD6417750RF240DV Datasheet, PDF (869/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 18 I/O Ports
Bit 2n + 1 (n = 0–3)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 4-bit
port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set
to output by bit PBnIO.
Bit 2n + 1: PBnPUP
0
1
Description
Bit m (m = 16–19) of 4-bit port is pulled up
Bit m (m = 16–19) of 4-bit port is not pulled up
(Initial value)
Bit 2n (n = 0–3)—Port I/O Control (PBnIO): Specifies whether each bit in the 4-bit port is an
input or an output.
Bit 2n: PBnIO
0
1
Description
Bit m (m = 16–19) of 4-bit port is an input
Bit m (m = 16–19) of 4-bit port is an output
(Initial value)
18.2.4 Port Data Register B (PDTRB)
Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit
in the 4-bit port. When a bit is set as an output, the value written to the PDTRB register is output
from the external pin. When a value is read from the PDTRB register while a bit is set as an input,
the external pin value sampled on the external bus clock is read. When a bit is set as an output, the
value written to the PDTRB register is read.
PDTRB is not initialized by a power-on or manual reset, or in standby mode, and retains its
contents.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
— PB19DT PB18DT PB17DT PB16DT
Initial value: 0
0
0
0
—
—
—
—
R/W: R
R
R
R
R/W R/W R/W R/W
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 817 of 1076