HD6417750RF240DV Datasheet, PDF (169/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 4 Caches
Figure 4.3 shows the configuration of the operand cache for the SH7750R.
Effective address
31
26 25
13 12 11 10 9
543 21 0
OIX
22
RAM area
determination
ORA
[13]
[12]
[11:5]
9
0
Address array
Tag
U
3
V
Longword (LW) selection
Data array
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
MMU
19
511 19 bits 1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
Compare
Read data
Write data
Hit signal
Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 117 of 1076