HD6417750RF240DV Datasheet, PDF (903/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 20 User Break Controller (UBC)
Section 20 User Break Controller (UBC)
20.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. When break
conditions are set in the UBC, a user break interrupt is generated according to the contents of the
bus cycle generated by the CPU. This function makes it easy to design an effective self-
monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-
circuit emulator.
20.1.1 Features
The UBC has the following features.
• Two break channels (A and B)
User break interrupts can be generated on independent conditions for channels A and B, or on
sequential conditions (sequential break setting: channel A → channel B).
• The following can be set as break compare conditions:
⎯ Address (selection of 32-bit virtual address and ASID for comparison):
Address: All bits compared/lower 10 bits masked/lower 12 bits masked/lower 16 bits
masked/lower 20 bits masked/all bits masked
ASID: All bits compared/all bits masked
⎯ Data (channel B only, 32-bit mask capability)
⎯ Bus cycle: Instruction access/operand access
⎯ Read/write
⎯ Operand size: Byte/word/longword/quadword
• An instruction access cycle break can be effected before or after the instruction is executed.
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Sep 24, 2013
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