HD6417750RF240DV Datasheet, PDF (1082/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Appendix C Mode Pin Settings
SH7750, SH7750S, SH7750R Group
• Clock Operating Modes (SH7750R)
External
Clock
Pin Combination
Operating
Mode
MD2 MD1 MD0
PLL1
Frequency
(vs. Input Clock)
CPU Bus Peripheral FRQCR
PLL2 Clock Clock Module Clock Initial Value
0
0
0
0
On (×12) On 12
3
3
H'0E1A
1
1
On (×12) On 12
3/2 3/2
H'0E2C
2
1
0
On (×6) On 6
2
1
H'0E13
3
1
On (×12) On 12
4
2
H'0E13
4
1
0
0
On (×6) On 6
3
3/2
H'0E0A
5
1
On (×12) On 12
6
3
H'0E0A
6
1
0
Off (×6) Off 1
1/2 1/2
H'0808
Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f ) and CKIO clock output (f ) in section 22.3.1, Clock and Control Signal
EX
OP
Timing.
(2) Area 0 Bus Width
MD6
0
1
Pin Value
MD4
MD3
0
0
1
1
0
1
0
0
1
1
0
1
Bus Width
64 bits
8 bits
16 bits
32 bits
64 bits
8 bits
16 bits
32 bits
Memory Type
MPX interface
Reserved (setting prohibited)
Reserved
MPX interface
SRAM interface
SRAM interface
SRAM interface
SRAM interface
Page 1030 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013