HD6417750RF240DV Datasheet, PDF (867/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 18 I/O Ports
Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16-
bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin
set to output by bit PBnIO.
Bit 2n + 1: PBnPUP
0
1
Description
Bit m (m = 0–15) of 16-bit port is pulled up
Bit m (m = 0–15) of 16-bit port is not pulled up
(Initial value)
Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port is an
input or an output.
Bit 2n: PBnIO
0
1
Description
Bit m (m = 0–15) of 16-bit port is an input
Bit m (m = 0–15) of 16-bit port is an output
(Initial value)
18.2.2 Port Data Register A (PDTRA)
Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit
in the 16-bit port. When a bit is set as an output, the value written to the PDTRA register is output
from the external pin. When a value is read from the PDTRA register while a bit is set as an input,
the external pin value sampled on the external bus clock is read. When a bit is set as an output, the
value written to the PDTRA register is read.
PDTRA is not initialized by a power-on or manual reset, or in standby mode, and retains its
contents.
Bit: 15
14
13
12
11
10
9
PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT PB9DT
Initial value: —
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W
8
PB8DT
—
R/W
Bit: 7
PB7DT
Initial value: —
R/W: R/W
6
PB6DT
—
R/W
5
PB5DT
—
R/W
4
PB4DT
—
R/W
3
PB3DT
—
R/W
2
PB2DT
—
R/W
1
PB1DT
—
R/W
0
PB0DT
—
R/W
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 815 of 1076