HD6417750RF240DV Datasheet, PDF (316/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 9 Power-Down Modes
SH7750, SH7750S, SH7750R Group
Bit 0—Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication
interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is
stopped when the MSTP0 bit is set to 1.
Bit 0: MSTP0
0
1
Description
SCI operates
SCI clock supply is stopped
(Initial value)
9.2.2 Peripheral Module Pin High Impedance Control
When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go
to the high-impedance state in standby mode.
• Relevant Pins
SCI related pins
DMA related pins
MD0/SCK
MD7/TXD
CTS2
DACK0
DACK1
MD1/TXD2
MD8/RTS2
DRAK0
DRAK1
• Other Information
The setting in this register is invalid when the above pins are used as port output pins.
For details of pin states, see Appendix E, Pin Functions.
Page 264 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013