HD6417750RF240DV Datasheet, PDF (550/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
CKIO
A25–A5
T1 TB2 TB1 TB2 TB1 TB2 TB1 T2
A4–A0
CSn
RD/WR
RD
D63–D0
(read)
BS
RDY
DACKn
(SA: IO ← memory)
Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed.
2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.47 Burst ROM Basic Access Timing
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Sep 24, 2013