HD6417750RF240DV Datasheet, PDF (552/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
CKIO
A25–A5
TS1 T1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 T2 TH1
A4–A0
CSn
RD/WR
RD
D63–D0
(read)
BS
RDY
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.49 Burst ROM Wait Access Timing
13.3.7 PCMCIA Interface
In this LSI, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory
space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA
specification version 4.2 (PCMCIA2.1).
Figure 13.50 shows an example of PCMCIA card connection to this LSI. To enable active
insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a
3-state buffer must be connected between this LSI's bus interface and the PCMCIA cards.
As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications,
this LSI supports only a little-endian mode PCMCIA interface.
In the SH7750, the PCMCIA interface area can only be accessed when the MMU is used. The
PCMCIA interface memory space can be set in page units and there is a choice of 8-bit common
memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O
space, 16-bit I/O space, or dynamic bus sizing, according to the accessed SA2 to SA0 bits.
The setting for wait cycles during a bus access can also be made in MMU page units. When the
TC bit to be accessed is cleared to 0, bits A5W2 to A5W0 in wait control register 2 (WCR2), and
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013