HD6417750RF240DV Datasheet, PDF (281/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 7 Instruction Set
4xIck is four or eight, respectively. Therefore, the affected codes are those occurring in
“the four words (or eight words) of data following the instruction.”
Workarounds: To prevent the problem, use either of workarounds a. or b. below.
a. Include a NOP instruction in the eight words of data following each TRAPA instruction,
SLEEP instruction, or undefined instruction code H'FFFD.
b. Include an OR R0,R0 instruction in the five words of data following each TRAPA instruction,
SLEEP instruction, or undefined instruction code H'FFFD. This workaround also applies to
cases where “the eight words of data following the … instruction … contain H'Fxxx,” as
mentioned in condition 4. b., because two OR instructions are never executed simultaneously,
so a minimum of 5xIck is required for execution.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 229 of 1076