HD6417750RF240DV Datasheet, PDF (759/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 15 Serial Communication Interface (SCI)
In multiprocessor mode serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR1 in LSB-to-MSB order.
3. If the MPIE bit is 1, MPIE is cleared to 0 when a 1 is received in the multiprocessor bit
position. If the multiprocessor bit is 0, the MPIE bit is not changed.
4. If the MPIE bit is 0, RDRF is checked at the stop bit position, and if RDRF is 1 the overrun
error bit is set. If the stop bit is not 0, the framing error bit is set. If RDRF is 0, the value in
SCRSR1 is transferred to SCRDR1, and if the stop bit is 0, RDRF is set to 1.
15.3.4 Operation in Synchronous Mode
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making
it suitable for high-speed serial communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 15.17 shows the general format for synchronous serial communication.
*
Serial clock
One unit of transfer data (character or frame)
*
LSB
Serial data Don't care Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
Bit 7 Don't care
Note: * High except in continuous transmission/reception
Figure 15.17 Data Format in Synchronous Communication
In synchronous serial communication, data on the transmission line is output from one falling edge
of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial
clock.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 707 of 1076