 English |
|
|
|
|
|
|
|
| HD6417750RF240DV Datasheet, PDF (535/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series | |||
| |||
| ◁ |
SH7750, SH7750S, SH7750R Group
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63âD0
(read)
BS
CKE
Tc1_A
H/L
c_A
Section 13 Bus State Controller (BSC)
Tc1_B
H/L
c_B
a1
a2
a3
a4
b1
b2
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding
Burst Read Cycle
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 483 of 1076
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese