HD6417750RF240DV Datasheet, PDF (264/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 7 Instruction Set
SH7750, SH7750S, SH7750R Group
Addressing Instruction
Mode
Format
Effective Address Calculation Method
Calculation
Formula
Register
@(disp:4, Rn)
indirect with
displacement
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
Byte: Rn +
disp → EA
Word: Rn +
disp × 2 → EA
Rn
disp
(zero-extended)
Longword:
Rn + disp × 4
+
Rn + disp × 1/2/4 → EA
×
Indexed
register
indirect
@(R0, Rn)
1/2/4
Effective address is sum of register Rn and R0
contents.
Rn
+
Rn + R0
Rn + R0 → EA
GBR indirect @(disp:8,
with
GBR)
displacement
R0
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
Byte: GBR +
disp → EA
Word: GBR +
disp × 2 → EA
GBR
disp
(zero-extended)
+
GBR
+ disp × 1/2/4
Longword:
GBR + disp ×
4 → EA
×
1/2/4
Indexed GBR @(R0, GBR) Effective address is sum of register GBR and R0
indirect
contents.
GBR
+
GBR + R0
GBR + R0 →
EA
R0
Page 212 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013