HD6417750RF240DV Datasheet, PDF (923/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 20 User Break Controller (UBC)
SL.BL
Pre-
Execution
Instruction
Access
0→0
A
1→0
M
0→1
A
1→1
M
Legend:
A: Accepted
M: Masked
Post-
Execution
Instruction
Access
A
M
M
M
Pre-
Execution
Instruction
Access
A
M
A
M
Post-
Execution
Instruction
Access
A
M
M
M
Operand
Access
(Address/Data)
A
A
M
M
e. In the case of an RTE delay slot
The BL bit value before execution of a delay slot instruction is the same as the BL bit value
before execution of an RTE instruction. The BL bit value after execution of a delay slot
instruction is the same as the first BL bit value for the first instruction executed on
returning by means of an RTE instruction (the same as the value of the BL bit in SSR
before execution of the RTE instruction).
f. If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit
before execution of the first instruction of the exception handling routine is 1.
4. If channels A and B both match independently at virtually the same time, and, as a result, the
SPC value is the same for both user break interrupts, only one user break interrupt is generated,
but both the CMFA bit and the CMFB bit are set. For example:
110 Instruction (post-execution instruction break on channel A) → SPC = 112, CMFA = 1
112 Instruction (pre-execution instruction break on channel B) → SPC = 112, CMFB = 1
5. The PCBA or PCBB bit in BRCR is invalid for an instruction access break setting.
6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel
B condition match. For example: A → A → B (user break generated) → B (no break
generated)
7. In the event of contention between a re-execution type exception and a post-execution break in
a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit
may or may not be set to 1 when the break condition occurs.
8. A post-execution break is classified as a completion type exception. Consequently, in the event
of contention between a completion type exception and a post-execution break, the post-
execution break is suppressed in accordance with the priorities of the two events. For example,
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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