HD6417750RF240DV Datasheet, PDF (26/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

20.3.6 Condition Match Flag Setting............................................................................... 868
20.3.7 Program Counter (PC) Value Saved ..................................................................... 868
20.3.8 Contiguous A and B Settings for Sequential Conditions ...................................... 869
20.3.9 Usage Notes .......................................................................................................... 870
20.4 User Break Debug Support Function ................................................................................. 872
20.5 Examples of Use ................................................................................................................ 874
20.6 User Break Controller Stop Function................................................................................. 876
20.6.1 Transition to User Break Controller Stopped State............................................... 876
20.6.2 Cancelling the User Break Controller Stopped State............................................ 876
20.6.3 Examples of Stopping and Restarting the User Break Controller......................... 877
Section 21 High-performance User Debug Interface (H-UDI) ......................... 879
21.1 Overview............................................................................................................................ 879
21.1.1 Features................................................................................................................. 879
21.1.2 Block Diagram...................................................................................................... 879
21.1.3 Pin Configuration.................................................................................................. 881
21.1.4 Register Configuration.......................................................................................... 882
21.2 Register Descriptions......................................................................................................... 883
21.2.1 Instruction Register (SDIR) .................................................................................. 883
21.2.2 Data Register (SDDR) .......................................................................................... 885
21.2.3 Bypass Register (SDBPR) .................................................................................... 886
21.2.4 Interrupt Source Register (SDINT) (SH7750R Only) .......................................... 886
21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) ........................................... 887
21.3 Operation ........................................................................................................................... 891
21.3.1 TAP Control ......................................................................................................... 891
21.3.2 H-UDI Reset ......................................................................................................... 892
21.3.3 H-UDI Interrupt .................................................................................................... 892
21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS)
(SH7750R Only)................................................................................................... 893
21.4 Usage Notes ....................................................................................................................... 893
Section 22 Electrical Characteristics ................................................................. 895
22.1 Absolute Maximum Ratings .............................................................................................. 895
22.2 DC Characteristics ............................................................................................................. 896
22.3 AC Characteristics ............................................................................................................. 920
22.3.1 Clock and Control Signal Timing ......................................................................... 922
22.3.2 Control Signal Timing .......................................................................................... 946
22.3.3 Bus Timing ........................................................................................................... 950
22.3.4 Peripheral Module Signal Timing....................................................................... 1003
22.3.5 AC Characteristic Test Conditions ..................................................................... 1015
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013