HD6417750RF240DV Datasheet, PDF (413/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Name
Data enable 0
Signals
I/O
WE0/CAS0/ O
DQM0
Data enable 1
WE1/CAS1/ O
DQM1
Data enable 2
WE2/CAS2/ O
DQM2/ICIORD
Data enable 3
WE3/CAS3/ O
DQM3/ICIOWR
Data enable 4
WE4/CAS4/ O
DQM4
Section 13 Bus State Controller (BSC)
Description
When setting synchronous DRAM interface:
selection signal for D7–D0
When setting DRAM interface: CAS signal for
D7–D0
When setting MPX interface: high-level output
In other cases: write strobe signal for D7–D0
When setting synchronous DRAM interface:
selection signal for D15–D8
When setting DRAM interface: CAS signal for
D15–D8
When setting PCMCIA interface: write strobe signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D15–D8
When setting synchronous DRAM interface:
selection signal for D23–D16
When setting DRAM interface: CAS signal for
D23–D16
When setting PCMCIA interface: ICIORD signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D23–D16
When setting synchronous DRAM interface:
selection signal for D31–D24
When setting DRAM interface: CAS signal for
D31–D24
When setting PCMCIA interface: ICIOWR signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D31–D24
When setting synchronous DRAM interface:
selection signal for D39–D32
When setting DRAM interface: CAS signal for
D39–D32
When setting MPX interface: high-level output
In other cases: write strobe signal for D39–D32
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 361 of 1076