HD6417750RF240DV Datasheet, PDF (495/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
SH7750, SH7750S, SH7750R
A16
A0
CSn
RD
D7
D0
WE0
Section 13 Bus State Controller (BSC)
128K × 8-bit
SRAM
A16
A0
CS
OE
I/O7
I/O0
WE
Figure 13.10 Example of 8-Bit Data Width SRAM Connection
Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 13.2.6, Wait
Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait
timing shown in figure 13.11.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 443 of 1076