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HD6417750RF240DV Datasheet, PDF (518/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series | |||
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Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Byte specification is performed by DQM0 to DQM7. A read/write is performed for the byte for
which the corresponding DQM signal is low. When the bus width is 64 bits, in big-endian mode
DQM7 specifies an access to address 8n, and DQM0 specifies an access to address 8n + 7. In
little-endian mode, DQM7 specifies an access to address 8n + 7, and DQM0 specifies an access to
address 8n.
Figures 13.26 and 13.27 show examples of the connection of 16M Ã 16-bit synchronous DRAMs.
SH7750, SH7750S, SH7750R
A12âA3
CKIO
CKE
CS3
RAS
CASS
RD/WR
D63âD48
DQM7
DQM6
512K à 16-bit à 2-bank
synchronous DRAM
A9âA0
CLK
CKE
CS
RAS
CAS
WE
I/O15âI/O0
DQMU
DQML
D47âD32
DQM5
DQM4
A9âA0
CLK
CKE
CS
RAS
CAS
WE
I/O15âI/O0
DQMU
DQML
D31âD16
DQM3
DQM2
A9âA0
CLK
CKE
CS
RAS
CAS
WE
I/O15âI/O0
DQMU
DQML
D15âD0
DQM1
DQM0
A9âA0
CLK
CKE
CS
RAS
CAS
WE
I/O15âI/O0
DQMU
DQML
Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3)
Page 466 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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