HD6417750RF240DV Datasheet, PDF (1113/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Appendix G Prefetching of Instructions and its Side Effects
Appendix G Prefetching of Instructions and its Side Effects
This LSI incorporates an on-chip buffer for holding instructions that have been read ahead of their
execution (prefetching of instructions). Therefore, do not allocate programs to memory in such a
way that instructions are in the last 20 bytes of any memory space. If a program is allocated in
such a way, the prefetching of instructions may lead to a bus access for reading an instruction
from beyond the memory space. The following shows a case in which such bus access is a
problem.
Address
Area 0
Area 1
H'03FFFFF8
H'03FFFFFA
H'03FFFFFC
H'03FFFFFE
H'04000000
H'04000002
......
ADD R1,R4
JMP @R2
NOP
NOP
PC (Program counter)
Address of instruction for prefetching
Figure G.1 Instruction Prefetch
Figure G.1 depicts a case in which the instruction (ADD) indicated by the program counter and the
instruction at the address H'04000002 are fetched simultaneously. The program is assumed to
branch to a region other than area 1 after the subsequent JMP instruction and delay slot instruction
have been executed.
In this case, a bus access to area 1 (instruction prefetch), which is not visible in the program flow,
may occur.
1. Side effects of the prefetching of instructions
a. An external bus access caused by an instruction prefetch may cause malfunctions in
external devices, such as FIFOs, that are connected to the region accessed.
b. If no device responds to an external bus request that is triggered by an instruction prefetch,
execution may hang.
2. Methods of preventing the invalid prefetching of instructions
a. Use an MMU.
b. Do not allocate programs so that they run into the last 20-byte region of any memory space.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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