HD6417750RF240DV Datasheet, PDF (197/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 4 Caches
4.7.4 SQ Protection
Determination of an exception in a write to an SQ or transfer to external memory (PREF
instruction) is performed as follows according to whether the MMU is on or off. In the SH7750 or
SH7750S, if an exception occurs in an SQ write, the SQ contents may be corrupted. In the
SH7750R, original SQ contents are guaranteed. If an exception occurs in transfer from an SQ to
external memory, the transfer to external memory will be aborted.
• When MMU is on
Operation is in accordance with the address translation information recorded in the UTLB, and
MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read
type for transfer from the SQs to external memory (PREF instruction), and a TLB miss
exception, protection violation exception, or initial page write exception is generated.
However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address
error will be flagged in user mode even if address translation is successful.
• When MMU is off
Operation is in accordance with MMUCR.SQMD.
0: Privileged/user access possible
1: Privileged access possible
If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will
be flagged.
4.7.5 Reading the SQs (SH7750R Only)
In the SH7750R, a load instruction may be executed in the privileged mode to read the contents of
the SQs from the address range of H'FF001000 to H'FF00103C in the P4 area. Only longword
access is possible.
[31:6]
[5]
[4:2]
[1:0]
: H'FF001000 : Store queue specification
: 0/1
: 0: SQ0 specification, 1: SQ1 specification
: LW specification : Specification of longword position in SQ0 or SQ1
: 00
: Fixed at 0
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 145 of 1076