HD6417750RF240DV Datasheet, PDF (612/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify
incrementing/decrementing of the DMA transfer source address. The specification of these bits is
ignored when data is transferred from an external device to external memory in single address
mode. For channel 0, in DDT mode these bits are set to SM1 = 0 and SM0 = 1 with the DTR
format.
Bit 13: SM1
0
1
Bit 12: SM0
0
1
0
1
Description
Source address fixed
(Initial value)
Source address incremented (+1 in 8-bit transfer, +2 in 16-bit
transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-
byte burst transfer)
Source address decremented (–1 in 8-bit transfer, –2 in 16-bit
transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32-
byte burst transfer)
Setting prohibited
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013