HD6417750RF240DV Datasheet, PDF (817/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 16 Serial Communication Interface with FIFO (SCIF)
Serial Data Reception: Figure 16.10 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
1. Receive error handling and
break detection: Read the DR,
ER, and BRK flags in
Read ER, DR, BRK flags in
SCFSR2, and the ORER flag
SCFSR2 and ORER
in SCLSR2, to identify any
flag in SCLSR2
error, perform the appropriate
error handling, then clear the
DR, ER, BRK, and ORER
ER or DR or BRK or ORER
Yes
= 1?
flags to 0. In the case of a
framing error, a break can also
be detected by reading the
value of the RxD2 pin.
No
Error handling _{2. SCIF status check and receive}
data read : Read SCFSR2 and
Read RDF flag in SCFSR2
check that RDF = 1, then read
the receive data in SCFRDR2,
No
RDF = 1?
read 1 from the RDF flag, and
then clear the RDF flag to 0.
The transition of the RDF flag
Yes
from 0 to 1 can also be
identified by an RXI interrupt.
Read receive data in
SCFRDR2, and clear RDF
flag in SCFSR2 to 0
3. Serial reception continuation
procedure: To continue serial
reception, read at least the
receive trigger set number of
No
All data received?
receive data bytes from
SCFRDR2, read 1 from the
RDF flag, then clear the RDF
Yes
flag to 0. The number of
Clear RE bit in SCSCR2 to 0
receive data bytes in
SCFRDR2 can be ascertained
by reading the lower bits of
End of reception
SCFDR2.
Figure 16.10 Sample Serial Reception Flowchart (1)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 765 of 1076