HD6417750RF240DV Datasheet, PDF (838/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 17 Smart Card Interface
SH7750, SH7750S, SH7750R Group
I/O data
TXI
(TEND interrupt)
Ds Da Db Dc Dd De Df Dg Dh Dp DE
Guard
time
12.5 etu
11.0 etu
GM = 0
GM = 1
Note: etu: Elementary Time Unit (time for transfer for 1 bit)
Figure 17.4 TEND Generation Timing
Bit Rate Register (SCBRR1) Setting: SCBRR1 is used to set the bit rate. See section 17.3.5,
Clock, for the method of calculating the value to be set.
Serial Control Register (SCSCR1) Settings: The function of the TIE, RIE, TE, and RE bits is
the same as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details.
The CKE1 and CKE0 bits specify the clock output state. See section 17.3.5, Clock, for details.
Smart Card Mode Register (SCSCMR1) Settings: The SDIR bit and SINV bit are both cleared
to 0 if the IC card is of the direct convention type, and both set to 1 if of the inverse convention
type.
The SMIF bit is set to 1 when the smart card interface is used.
Figure 17.5 shows examples of register settings and the waveform of the start character for the two
types of IC card (direct convention and inverse convention).
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to
state A, and transfer is performed in LSB-first order. The start character data in this case is H'3B.
The parity bit is 1 since even parity is stipulated for the smart card.
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data in this case is H'3F.
The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013