HD6417750RF240DV Datasheet, PDF (14/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode ...................... 85
3.3.7 Address Space Identifier (ASID) ............................................................................ 85
3.4 TLB Functions ..................................................................................................................... 86
3.4.1 Unified TLB (UTLB) Configuration ...................................................................... 86
3.4.2 Instruction TLB (ITLB) Configuration................................................................... 90
3.4.3 Address Translation Method................................................................................... 90
3.5 MMU Functions................................................................................................................... 93
3.5.1 MMU Hardware Management................................................................................ 93
3.5.2 MMU Software Management ................................................................................. 93
3.5.3 MMU Instruction (LDTLB).................................................................................... 93
3.5.4 Hardware ITLB Miss Handling .............................................................................. 94
3.5.5 Avoiding Synonym Problems................................................................................. 95
3.6 MMU Exceptions................................................................................................................. 96
3.6.1 Instruction TLB Multiple Hit Exception................................................................. 96
3.6.2 Instruction TLB Miss Exception............................................................................. 96
3.6.3 Instruction TLB Protection Violation Exception .................................................... 98
3.6.4 Data TLB Multiple Hit Exception .......................................................................... 98
3.6.5 Data TLB Miss Exception ...................................................................................... 99
3.6.6 Data TLB Protection Violation Exception............................................................ 100
3.6.7 Initial Page Write Exception................................................................................. 101
3.7 Memory-Mapped TLB Configuration ............................................................................... 102
3.7.1 ITLB Address Array ............................................................................................. 103
3.7.2 ITLB Data Array 1................................................................................................ 104
3.7.3 ITLB Data Array 2................................................................................................ 105
3.7.4 UTLB Address Array............................................................................................ 106
3.7.5 UTLB Data Array 1 .............................................................................................. 107
3.7.6 UTLB Data Array 2 .............................................................................................. 108
3.8 Usage Notes ....................................................................................................................... 109
Section 4 Caches................................................................................................ 111
4.1 Overview............................................................................................................................ 111
4.1.1 Features................................................................................................................. 111
4.1.2 Register Configuration.......................................................................................... 113
4.2 Register Descriptions......................................................................................................... 114
4.3 Operand Cache (OC) ......................................................................................................... 116
4.3.1 Configuration........................................................................................................ 116
4.3.2 Read Operation ..................................................................................................... 120
4.3.3 Write Operation .................................................................................................... 121
4.3.4 Write-Back Buffer ................................................................................................ 122
4.3.5 Write-Through Buffer........................................................................................... 122
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013