HD6417750RF240DV Datasheet, PDF (505/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
Wait State Control: As the clock frequency increases, it becomes impossible to complete all
states in one cycle as in basic access. Therefore, provision is made for state extension by using the
setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in
figure 13.18. Additional Tpc cycles (cycles used to secure the RAS precharge time) can be
inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from
RAS assertion to CAS assertion can be set to between 2 and 5 by inserting Trw cycles by means of
the RCD bit in MCR. Also, the number of cycles from CAS assertion to the end of the access can
be varied between 1 and 16 according to the setting of A2W2 to A2W0 or A3W2 to A3W0 in
WCR2.
CKIO
Tr1
Tr2
Trw
Tc1
Tcw
Tc2
Tpc
Tpc
A25–A0
CSn
RD/WR
Row
Column
RAS
CAS
D63–D0
(read)
D63–D0
(write)
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.18 DRAM Wait State Timing
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 453 of 1076