HD6417750RF240DV Datasheet, PDF (812/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
SH7750, SH7750S, SH7750R Group
Data Transfer Operations
SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE
bits in SCSCR2 to 0, then initialize the SCIF as described below.
When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making
the change using the following procedure. When the TE bit is cleared to 0, SCTSR2 is initialized.
Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2, SCFTDR2, or
SCFRDR2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND
flag in SCFSR2 has been set. TEND can also be cleared to 0 during transmission, but the data
being transmitted will go to the mark state after the clearance. Before setting TE again to start
transmission, the TFRST bit in SCFCR2 should first be set to 1 to reset SCFTDR2.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation will be unreliable in this case.
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Sep 24, 2013