HD6417750RF240DV Datasheet, PDF (36/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Figure 14.34 Handshake Protocol without Use of Data Bus
(Channel 0 On-Demand Data Transfer)................................................................. 617
Figure 14.35 Read from Synchronous DRAM Precharge Bank ................................................. 618
Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ..................... 618
Figure 14.37 Read from Synchronous DRAM (Row Hit) .......................................................... 619
Figure 14.38 Write to Synchronous DRAM Precharge Bank..................................................... 619
Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)......................... 620
Figure 14.40 Write to Synchronous DRAM (Row Hit).............................................................. 620
Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer .......................................... 621
Figure 14.42 DDT Mode Setting ................................................................................................ 622
Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device →
External Bus Data Transfer ................................................................................... 622
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus →
External Device Data Transfer .............................................................................. 623
Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word,
Longword, Quadword/External Bus → External Device Data Transfer ............... 624
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word,
Longword, Quadword/External Device → External Bus Data Transfer ............... 625
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Request to Channels 1–3 Using Data Bus ............................................................. 626
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus →
External Device Data Transfer/ Direct Data Transfer Request to Channel 2
without Using Data Bus......................................................................................... 627
Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer/Direct Data Transfer Request to Channel 2 ............................................ 628
Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer/Direct Data Transfer Request to Channel 2 ............................................ 629
Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2....... 630
Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2....... 631
Figure 14.53 Block Diagram of the DMAC ............................................................................... 635
Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)............................................ 646
Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 650
Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte
Block Transfer/On-Demand Data Transfer on Channel 4 ..................................... 651
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Sep 24, 2013