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| HD6417750RF240DV Datasheet, PDF (925/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series | |||
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SH7750, SH7750S, SH7750R Group
Section 20 User Break Controller (UBC)
Exception/interrupt
generation
Hardware operation
SPC â PC
SSR â SR
SR.BL â B'1
SR.MD â B'1
SR.RB â B'1
Exception
Exception/
interrupt/trap?
Interrupt
EXPEVT â exception code INTEVT â interrupt code
Trap
EXPEVT â H'160
TRA â TRAPA (imm)
SGR â R15
No
Yes
Reset exception?
Yes
(BRCR.UBDE == 1) &&
No
(user break exception)?
PC â DBR
PC â VBR + vector offset
PC â H'A0000000
Debug program
R15 â SGR
(STC instruction)
Exception service routine
Execute RTE instruction
PC â SPC
SR â SSR
End of exception
operations
Figure 20.2 User Break Debug Support Function Flowchart
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 873 of 1076
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